View AD7884_2029853.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD7884/ad7885 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 lc 2 mos 16-bit, high-speed sampling adcs 3v in f AD7884 timer control dgnd cs rd busy db15 agnds agndf av dd gnd db0 convst v dd 9 9 9 16 16 v ref r3 3k c1 sw1 sw2 9-bit adc latch + alu o u t p u t d r i v e r s 16-bit accurate dac r2 3k 3v in s r1 5k r5 4k a2 sw3 r6 2k r7 2k r8 2k 5v in f 5v in s av ss v ss v ref+ fv ref+ sv inv v ref r4 4k a1 ad7885 timer control dgnd cs rd busy db7 agnds agndf av dd gnd db0 convst v dd 9 9 9 16 8 v ref r3 3k c1 sw1 sw2 9-bit adc latch + alu o u t p u t d r i v e r s 16-bit accurate dac r2 3k 3v in r1 5k r5 4k a2 sw3 r6 2k r7 2k r8 2k 5v in f 5v in s av ss v ss v ref+ fv ref+ sv inv v ref r4 4k hben a1 features monolithic construction fast conversion: 5.3 s high throughput: 166 ksps low power: 250 mw applications automatic test equipment medical instrumentation industrial control data acquisition systems robotics general description the AD7884/ad7885 is a 16-bit monolithic analog-to-digital converter with internal sample-and-hold and a conversion time of 5.3 s. the maximum throughput rate is 166 ksps. it uses a two-pass flash architecture to achieve this speed. two input ranges are available: 5 v and 3 v. conversion is initiated by the convst signal. the result can be read into a microprocessor using the cs and rd inputs on the device. the AD7884 has a 16-bit parallel reading structure while the ad7885 has a byte reading structure. the conversion result is in two? complement code. the AD7884/ad7885 has its own internal oscillator which controls conversion. it runs from 5 v supplies and needs a v ref+ of 3 v. the AD7884 is available in a 40-lead cerdip package and in a 44-lead plcc package. the ad7885 is available in a 28-lead cerdip package and the ad7885a is available in a 44-lead plcc package. functional block diagrams
rev. d C2C AD7884/ad7885/ad7885a?pecifications (v dd = 5 v 5%, v ss = ? v 5%, v ref +s = 3 v; agnd = dgnd = gnd = 0 v; f sample = 166 khz. all specifications t min to t max , unless otherwise noted.) jab parameter version 1, 2, 3 version 1, 2, 3 versions 1, 2, 3 unit test conditions/comments dc accuracy resolution 16 16 16 bits minimum resolution for which no missing codes are guaranteed 16 16 16 bits integral nonlinearity 0.0075 % fsr max typically 0.003% fsr positive gain error 0.1 0.03 0.03 % fsr typ ad7885an/bn: 0.1% typ positive gain error 0.05 % fsr max ad7885bn: 0.2% max gain tc 4 2 2 2 ppm fsr/ c typ bipolar zero error 0.05 0.05 0.05 % fsr typ bipolar zero error 0.15 % fsr max bipolar zero tc 4 8 8 8 ppm fsr/ c typ negative gain error 0.1 0.03 0.03 % fsr typ ad7885an/bn: 0.1% typ negative gain error 0.05 % fsr max ad7885bn: 0.2% max offset tc 4 2 2 2 ppm fsr/ c typ noise 120 120 120 v rms typ 78 v rms typical in 3 v input range dynamic performance signal to (noise + distortion) ratio 82 84 84 db min i nput signal: 5 v, 1 khz sine wave, typically 86 db 82 82 82 db typ input signal: 5 v, 12 khz sine wave total harmonic distortion ?4 ?8 ?8 db max input signal: 5 v, 1 khz sine wave ?4 ?4 ?4 db typ input signal: 5 v, 12 khz sine wave peak harmonic or spurious noise ?8 ?8 ?8 db max input signal: 5 v, 1 khz sine wave intermodulation distortion (imd) second order terms ?4 ?4 ?4 db typ f a = 11.5 khz, f b = 12 khz, f sample = 166 khz third order terms ?4 ?4 ?4 db typ f a = 11.5 khz, f b = 12 khz, f sample = 166 khz conversion time conversion time 5.3 5.3 5.3 s max acquisition time 2.5 2.5 2.5 s max throughput rate 166 166 166 ksps max there is an overlap between conversion and acquisition. analog input voltage range 5 5 5 volts 3 3 3 volts input current 4 4 4 ma max reference input reference input current 5 5 5 ma max v ref+ s = 3 v logic inputs input high voltage, v inh 2.4 2.4 2.4 v min v dd = 5 v 5% input low voltage, v inl 0.8 0.8 0.8 v max v dd = 5 v 5% input current, i in 10 10 10 a max input level = 0 v to v dd input capacitance, c in 4 10 10 10 pf max logic outputs output high voltage, v oh 4.0 4.0 4.0 v min i source = 40 a output low voltage, v ol 0.4 0.4 0.4 v max i sink = 1.6 ma db15?b0 floating-state leakage current 10 10 10 a max floating-state output capacitance 4 15 15 15 pf max power requirements v dd 5 5 5 v nom 5% for specified performance v ss ? ? ? v nom 5% for specified performance i dd 35 35 35 ma max typically 25 ma i ss 30 30 30 ma max typically 25 ma power supply rejection ratio ? gain/ ? v dd 86 86 86 db typ ? gain/ ? v ss 86 86 86 db typ power dissipation 325 325 325 mw max typically 250 mw notes 1 temperature ranges are as follows: j, a, b versions: ?0 c to +85 c. 2 v in = 5 v. 3 the ad7885aap has the same specs as the AD7884ap. the ad7885abp has the same specs as the AD7884bp. 4 sample tested to ensure compliance. specifications subject to change without notice.
rev. d AD7884/ad7885 C3C timing characteristics 1, 2 limit at 25 c limit at t min , t max parameter (all versions) (a, b, and j versions) unit conditions/comments t 1 50 50 ns min convst pulsewidth t 2 100 100 ns max convst to busy low delay t 3 0 0 ns min cs to rd setup time t 4 60 60 ns min rd pulsewidth t 5 0 0 ns min cs to rd hold time t 6 2 57 57 ns max data access time after rd t 7 3 5 5 ns min bus relinquish time after rd 50 50 ns max t 8 40 40 ns min new data valid before rising edge of busy t 9 10 80 ns min hben to rd setup time t 10 25 25 ns min hben to rd hold time t 11 60 60 ns min hben low pulse duration t 12 60 60 ns min hben high pulse duration t 13 55 70 ns max propagation delay from hben falling to data valid t 14 55 70 ns max propagation delay from hben rising to data valid notes 1 sample tested at 25 c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v. 2 t 6 is measured with the load circuit of figure 1 and defined as the time required for an output to cross 0.8 v or 2.4 v. 3 t 7 is derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 1. the meas ured number is then extrapolated back to remove the effects of charging or discharging the 100 pf capacitor. this means that the time, t 7 , quoted in the timing characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances. specifications subject to change without notice. (v dd = +5 v 5%, v ss = ? v 5%, agnd = dgnd = gnd = 0 v. see figures 2, 3, 4, and 5.) to output pin 2.1v c l 100pf 200 a i oh 1.6ma i ol figure 1. load circuit for access time and bus relinquish time
rev. d AD7884/ad7885 C4C t 6 t 2 cs rd data busy convst hi-z t 3 t 1 t 5 t 7 t convert t 4 hi-z data valid figure 2. AD7884 timing diagram, using cs and rd data old data valid new data valid busy convst t 1 t 2 t 8 t convert figure 3. AD7884 timing diagram, with cs and rd permanently low hben cs rd data busy convst hi-z hi-z db0 db7 db8 db15 hi-z t 2 data valid t 1 data valid t 9 t 10 t 3 t 5 t 6 t 7 t 4 t convert figure 4. ad7885 timing diagram, using cs and rd data busy hben convst t 1 t 11 t 12 t 2 t 8 t 13 t 14 t convert old data valid (db8 db15) new data valid (db8 db15) new data valid (db0 db7) new data valid (db8 db15) new data valid (db0 db7) figure 5. ad7885 timing diagram, with cs and rd permanently low
rev. d AD7884/ad7885 C5C ordering guide linearity temperature error snr package model range (% fsr) (db) option AD7884ap ?0 c to +85 c 84 p-44a AD7884bp ?0 c to +85 c 0.0075 84 p-44a ad7885aap ?0 c to +85 c 84 p-44a ad7885abp ?0 c to +85 c 0.0075 84 p-44a AD7884aq ?0 c to +85 c 84 q-40 AD7884bq ?0 c to +85 c 0.0075 84 q-40 ad7885jq ?0 c to +85 c 82 q-28 ad7885aq ?0 c to +85 c 84 q-28 ad7885bq ?0 c to +85 c 0.0075 84 q-28 note p = plastic leaded chip carrier (plcc); q = cerdip. absolute maximum ratings 1 v dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7 v av dd to agnd . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7 v v ss to agnd . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to ? v av ss to agnd . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to ? v agnd pins to dgnd . . . . . . . . . . . . ?.3 v to v dd + 0.3 v av dd to v dd 2 . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7 v av ss to v ss 2 . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to ? v gnd to dgnd . . . . . . . . . . . . . . . . . ?.3 v to v dd + 0.3 v v in s, v in f to agnd . . . . . . . . . . v ss ?0.3 v to v dd + 0.3 v v ref+ to agnd . . . . . . . . . . . . . . v ss ?0.3 v to v dd + 0.3 v v ref to agnd . . . . . . . . . . . . . . . v ss ?0.3 v to v dd + 0.3 v v inv to agnd . . . . . . . . . . . . . . . v ss ?0.3 v to v dd + 0.3 v digital inputs to dgnd . . . . . . . . . . . ?.3 v to v dd + 0.3 v digital outputs to dgnd . . . . . . . . . . ?.3 v to v dd + 0.3 v operating temperature range commercial plastic (a, b versions) . . . . . ?0 c to +85 c industrial cerdip (j, a, b versions) . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . . 300 c 28-lead cerdip ja thermal impedance . . . . . . . . . . . . . . . . . . . . 50.9 c/w jc thermal impedance . . . . . . . . . . . . . . . . . . . . . 8.3 c/w 40-lead cerdip ja thermal impedance . . . . . . . . . . . . . . . . . . . . 44.5 c/w 44-lead plcc ja thermal impedance . . . . . . . . . . . . . . . . . . . . 47.7 c/w jc thermal impedance . . . . . . . . . . . . . . . . . . . . 17.5 c/w power dissipation (any package) to 75 c . . . . . . . . 1000 mw degradation above 75 c by . . . . . . . . . . . . . . . . . . 10 mw/ c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 if the AD7884/ad7885 is being powered from separate analog and digital supplies, av ss should always come up before v ss . see figure 12 for a recommended protection circuit using schottky diodes. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD7884/ad7885 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. d AD7884/ad7885 C6C pin configurations cerdip plcc top view (not to scale) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 AD7884 rd cs c onvst v dd v ss gnd av ss v inv 3v in f 5v in s 5v in f av dd agndf agnds db0 db1 db2 db3 dgnd v ref+ s v ref+ f v dd db5 db6 db7 busy v ss v ss gnd 3v in s v ref db15 db12 db13 db14 db4 db8 db9 db10 db11 top view (not to scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ad7885 rd cs c onvst v dd v ss gnd av ss v ref 3v in 5v in s 5v in f av dd agndf agnds hben busy db0 db1 db2 db3 dgnd v inv v ref+ s v ref+ f db7 db4 db5 db6 6 5 4 3 2 1 44 43 42 41 40 pin 1 identifier top view (not to scale) 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 18 nc = no connect db12 db11 db10 db9 db8 nc dgnd v dd db7 db6 db5 5v in f agnds agndf av dd av ss nc gnd gnd v ss v ss v dd 5v in s 3v in f 3v in s v ref v inv nc v ref+ s convst cs rd v ss nc db0 db1 db2 db3 db4 busy v ref+ f db15 db14 db13 AD7884 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 pin 1 identifier top view (not to scale) 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 18 nc = no connect db7 db6 nc db5 db4 nc dgnd v dd db3 db2 db1 5v in f agnds agndf av dd av ss nc gnd gnd v ss v ss v dd 5v in s 3v in f 3v in s v ref v inv nc v ref+ s c onvst cs rd hben nc nc nc nc nc db0 busy v ref+ f nc nc nc ad7885a 19 20 21 22 23 24 25 26 27 28
rev. d AD7884/ad7885 C7C pin function description AD7884 ad7885 ad7885a description v inv v inv v inv this pin is connected to the inverting terminal of an op amp, as in figure 6, and allows the inversion of the supplied 3 v reference. v ref v ref v ref this is the negative reference input, and it can be obtained by using an external amplifier to invert the positive reference input. in this case, the amplifier output is connected to v ref? see figure 6. 3 v in s_ 3 v in s this is the analog input sense pin for the 3 volt analog input range on the AD7884 and ad7885a. 3 v in f_ 3 v in f this is the analog input force pin for the 3 volt analog input range on the AD7884 and ad7885a. when using this input range, the 5 v in f and 5 v in s pins should be tied to agnd. 3 v in this is the analog input pin for the 3 volt analog input range on the ad7885. when using this input range, the 5 v in f and 5 v in s pins should be tied to agnd. 5 v in s 5 v in s 5 v in s this is the analog input sense pin for the 5 volt analog input range on both the AD7884, ad7885 and ad7885a. 5 v in f 5 v in f 5 v in f this is the analog input force pin for the 5 volt analog input range on both the AD7884, ad7885 and ad7885a. when using this input range, the 3 v in f and 3 v in s pins should be tied to agnd. agnds agnds agnds this is the ground return sense pin for the 9-bit adc and the on-chip residue amplifier. agndf agndf agndf this is the ground return force pin for the 9-bit adc and the on-chip residue amplifier. av dd av dd av dd positive analog power rail for the sample-and-hold amplifier and the residue amplifier. av ss av ss av ss negative analog power rail for the sample-and-hold amplifier and the residue amplifier. gnd gnd gnd this is the ground return for sample-and-hold section. v ss v ss v ss negative supply for the 9-bit adc. v dd v dd v dd positive supply for the 9-bit adc and all device logic. convst convst convst this asynchronous control input starts conversion. cs cs cs chip select control input. rd rd rd read control input. this is used in conjunction with cs to read the conversion result from the device output latch. hben hben high byte enable. active high control input for the ad7885. it selects either the high or the low byte of the conversion for reading. busy busy busy busy output. the busy output goes low when conversion begins and stays low until it is completed, at which time it goes high. db0?b15 sixteen-bit parallel data word output on the AD7884. db0?b7 db0?b7 eight-bit parallel data byte output on the ad7885. dgnd dgnd dgnd ground return for all device logic. v ref+ fv ref+ fv ref+ f reference force input. v ref+ sv ref+ sv ref+ s reference sense input. the device operates from a 3 v reference.
rev. d AD7884/ad7885 C8C terminology integral nonlinearity this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. bipolar zero error this is the deviation of the midscale transition (all 0s to all 1s) from the ideal (agnd). positive gain error this is the deviation of the last code transition (01 . . . 110 to 01 . . . 111) from the ideal (+v ref+ s ?1 lsb), after bipolar zero error has been adjusted out. negative gain error this is the deviation of the first code transition (10 . . . 000 to 10 . . . 001) from the ideal (? ref+ s + 1 lsb), after bipolar zero error has been adjusted out. signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distortion) at the output of the a/d converter. the signal is the rms amplitude of the fundamental. noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quan- tization noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: s ignal to (noise + distortion) = ( 6.02 n + 1.76 ) db thus for an ideal 16-bit converter, this is 98 db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the AD7884/ad7885, it is defined as: thd ( db ) = 20 log v 2 2 + v 3 2 + v 4 2 + v 5 2 + v 6 2 v 1 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is deter- mined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation terms are those for which neither m or n are equal to zero. for example, the second order terms include (fa + fb) and (fa fb), while the third order terms include (2fa + fb), (2fa fb), (fa + 2fb) and (fa 2fb). the AD7884/ad7885 is tested using the cciff standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second and third order terms are of different significance. the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dbs. power supply rejection ratio this is the ratio, in dbs, of the change in positive gain error to the change in v dd or v ss . it is a dc measurement. operational diagram an operational diagram for the AD7884/ad7885 is shown in figure 6. it is set up for an analog input range of 5 v. if a 3 v input range is required, a1 should drive 3 v in s and 3 v in f with 5 v in s, 5 v in f being tied to system agnd. 3v in f 5v in f 5v +5v ad817 ad711 ad817 agnds agndf AD7884/ ad7885 ad845, ad817 or equivalent note: power supply decoupling not shown gnd dgnd v dd = +5v control inputs v inv v ref+ s v ref+ f v ref 3v in s 5v in s av ss v dd av dd v ss v in ad845, ad817 or equivalent ad780 2 6 8 4 10 f a1 a2 a3 a4 data outputs figure 6. AD7884/ad7885 operational diagram the chosen input buffer amplifier (a1) should have low noise and distortion and fast settling time for high bandwidth applica- tions. both the ad711 and the ad845 are suitable amplifiers. a2 is the force, sense amplifier for agnd. the agnds pin should be at zero potential. therefore, the amplifier must have a low input offset voltage and good noise performance. it must also have the ability to deal with fast current transients on the agnds pin. the ad817 has the required performance and is the recommended amplifier. if agnds and agndf are simply tied together to star ground instead of buffering, the snr and thd are not signifi- cantly degraded. however, dc specifications like inl, bipolar zero and gain error will be degraded.
rev. d AD7884/ad7885 C9C the required 3 v reference is derived from the ad780 and buffered by the high-speed amplifier a3 (ad845, ad817 or equivalent). a4 is a unity gain inverter which provides the 3 v negative reference. the gain setting resistors are on-chip and are factory trimmed to ensure precise tracking of v ref+ . figure 6 shows a3 and a4 as ad845s or ad817s. these have the ability to respond to the rapidly changing reference input impedance. circuit description analog input section the analog input section of the AD7884/ad7885 is shown in figure 7. it contains both the input signal conditioning and sample-and-hold amplifier. note that the analog input is truly benign. when sw1a goes open circuit to put the sha into the hold mode, sw1b is closed. this means that the input resis- tors, r1 and r2 are always connected to either virtual ground or true ground. r5 4k c1 sw1 a a1 3v in f to residue amplifier a2 to 9-bit adc v ref sw1 b r3 3k r6 2k r4 4k r2 5k r1 3k 3v in s 5v in f 5v in s a1 figure 7. AD7884/ad7885 analog input section when the 3 v in s and 3 v in f inputs are tied to 0 v, the input section has a gain of 0.6 and transforms an input signal of 5 volts to the required 3 volts. when the 5 v in s and 5 v in f inputs are grounded, the input section has a gain of 1 and so the analog input range is now 3 volts. resistors r4 and r5, at the amplifier output, further condition the 3 volts signal to be 0 volt to 3 volts. this is the required input for the 9-bit a/d converter section. with sw1a closed, the output of a1 follows the input (the sample-and-hold is in the track mode). on the rising edge of the convst pulse, sw1a goes open circuit, and capacitor c1 holds the voltage on the output of a1. the sample-and-hold is now in the hold mode. the aperture delay time for the sample- and-hold is nominally 50 ns. a/d converter section the AD7884/ad7885 uses a two-pass flash technique in order to achieve the required speed and resolution. when the convst control input goes from low to high, the sample-and-hold ampli- fier goes into the hold mode and a 0 v to 3 v signal is presented to the input of the 9-bit adc. the first phase of conversion generates the 9 msbs of the 16-bit result and tra nsfers these to the latch and alu combination. they are also fed back to the 9 msbs of the 16-bit dac. the 7 lsbs of the dac are per- manently l oaded with 0s. the dac output is subtracted from the analog input with the result being amplified and offset in the residue amplifier section. the signal at the output of a2 is proportional to the error between the first phase result and the actual analog input signal, and is digitized in the second conversion phase. this second phase begins when the 16-bit dac and the residue error amplifier have both settled. first, sw2 is turned off and sw3 is turned on. then, the sha section of the resi- due amplifier goes into hold mode. next sw2 is turned off and sw3 is turned on. the 9-bit result is transferred to the output latch and alu. an error correction algorithm now compensates for the offset inserted in the residue amplifier section and errors introduced in the first pass conversion and combines both results to give the 16-bit answer. 9 9 v ref r4 4k r5 4k sw2 sw3 r6 2k a2 9-bit adc latch + alu 16 0 to 3v 3v signal from input sha v ref+ f r7 2k r8 2k +3v 3v residue amp + sha 9 16-bit accurate dac v ref+ s v inv v ref figure 8. a/d converter section timing and control section figure 9 shows the timing and control sequence for the AD7884/ ad7885. when the part receives a convst pulse, the con- version begins. the input sample-and-hold goes into the hold mode 50 ns after the rising edge of convst and busy goes low. this is the first phase of conversion and takes 3.35 s to complete. the second phase of conversion begins when sw2 is turned off and sw3 turned on. the residue amplifier and sha section (a2 in figure 8) goes into hold mode at this point and allows the input sample-and-hold to go back into sample mode. thus, while the second phase of conversion is ongoing, the input sample-and-hold is also acquiring the input signal for the next conversion. this overlap between conversion and ac qui- sition allows throughput rates of 166 ksps to be achieved. convst busy hold sample input sha first phase 3.5 s tacq 2.5 s second phase first phase of conversion 1st 9-bit conversion dac settling time residue amplifier settling time second phase of conversion 2nd 9-bit conversion error correction output latch update 1.8 s figure 9. timing and control sequence
rev. d AD7884/ad7885 C10C analog input 3 v 5 v digital output in terms of fsr 2 range 3 range 4 code transition l +fsr/2 1 lsb 2.999908 4.999847 011 . . . 111 to 111 . . . 110 +fsr/2 2 lsbs 2.999817 4.999695 011 . . . 110 to 011 . . . 101 +fsr/2 3 lsbs 2.999726 4.999543 011 . . . 101 to 011 . . . 100 agnd + 1 lsb 0.000092 0.000153 000 . . . 001 to 000 . . . 000 agnd 0.000000 0.000000 000 . . . 000 to 111 . . . 111 agnd 1 lsb 0.000092 0.000153 111 . . . 111 to 111 . . . 110 (fsr/2 3 lsbs) 2.999726 4.999543 100 . . . 011 to 100 . . . 010 (fsr/2 2 lsbs) 2.999817 4.999695 100 . . . 010 to 100 . . . 001 (fsr/2 1 lsb) 2.999908 4.999847 100 . . . 001 to 100 . . . 000 notes 1 this table applies for v ref+ s = 3 v. 2 fsr (full-scale range) is 6 volts for the 3 v input range and 10 volts for the 5 v input range. 3 1 lsb on the 3 v range is fsr/2 16 and is equal to 91.5 v. 4 1 lsb on the 5 v range is fsr/2 16 and is equal to 152.6 v. using the AD7884/ad7885 analog input ranges the AD7884/ad7885 can be set up to have either a 3 volts analog input range or a 5 volts analog input range. figures 10 and 11 show the necessary corrections for each of these. the output code is two s complement and the ideal code table for both input ranges is shown in table i. reference considerations th e AD7884/ad7885 operates from a 3 volt reference. this can be derived simply using the ad780 as shown in figure 6. 5v in s 5v in f 3v in s 3v in f v inv a1 figure 10. 5 v input range connection 3v in s 3v in f 5v in s 5v in f v inv a1 figure 11. 3 v input range connections the critical performance specification for a reference in a 16-bit application is noise. the reference pk-pk noise should be insig- nificant in comparison to the adc noise. the AD7884/ad7885 has a typical rms noise of 120 v. for example a reasonable target would be to keep the total rms noise less than 125 v. to do this the reference noise needs to be less than 35 v rms. in the 100 khz band, the ad780 noise is less than 30 v rms, making it a very suitable reference. the buffer amplifier used to drive the device v ref+ should have low enough noise performance so as not to affect the overall system noise requirement. the ad845 and ad817 achieve this. decoupling and grounding the AD7884 and ad7885a have one av dd pin and two v dd pins. they also have one av ss pin and three v ss pins. the ad7885 has one av dd pin, one v dd pin, one av ss pin and one v ss pin. figure 6 shows how a common +5 v supply should be used for the positive supply pins and a common 5 v supply for the negative supply pins. for decoupling purposes, the critical pins on both devices are the av dd and av ss pins. each of these should be decoupled to system agnd with 10 f tantalum and 0.1 f ceramic capaci- tors right at the pins. with the v dd and v ss pins, it is sufficient to decouple each of these with ceramic 1 f capacitors. agnds, agndf are the ground return points for the on-chip 9-bit adc. they should be driven by a buffer amplifier as shown in figure 6. if they are tied directly together and then to ground, there will be a marginal degradation in linearity performance. the gnd pin is the analog ground return for the on-chip lin- ear circuitry. it should be connected to system analog ground. the dgnd pin is the ground return for the on-chip digital circuitry. it should be connected to the ground terminal of the v dd and v ss supplies. if a common analog supply is used for av dd and v dd then dgnd should be connected to the com- mon ground point. power supply sequencing av dd and v dd are connected to a common substrate and there is typically 17 ? resistance between them. if they are powered by separate 5 v supplies, then these should come up simulta- neously. otherwise, the one that comes up first will have to drive 5 v into a 17 ? load for a short period of time. however, the standard short-circuit protection on regulators like the 7800 series will ensure that there is no possibility of damage to the driving device. av ss should always come up either before or at the same time as v ss . if this cannot be guaranteed, schottky diodes should be used to ensure that v ss never exceeds av ss by more than 0.3 v. arranging the power supplies as in figure 6 and using the recommended decoupling ensures that there are no power supply sequencing issues as well as giving the specified noise performance. av dd v dd av ss v ss +5v +5v 5v 5v AD7884/ad7885 hp5082-2810 or equivalent figure 12. schottky diodes used to protect against incorrect power supply sequencing table i. ideal output code table for the AD7884/ad7885
rev. d AD7884/ad7885 C11C AD7884/ad7885 performance linearity the linearity of the AD7884/ad7885 is determined by the on-chip 16-bit d/a converter. this is a segmented dac which is laser trimmed for 16-bit dnl performance to ensure that there are no missing codes in the adc transfer function. figure 13 shows a typical inl plot for the AD7884/ad7885. 0 16384 32768 49152 65535 output code 0 0.5 1.0 1.5 2.0 linearity error lsbs v dd = +5v v ss = 5v t a = +25 c figure 13. AD7884/ad7885 typical linearity performance noise in an a/d converter, noise exhibits itself as code uncertainty in dc applications and as the noise floor (in an fft, for example) in ac applications. in a sampling a/d converter like the AD7884/ad7885, all information about the analog input appears in the baseband from dc to 1/2 the sampling frequency. an antialiasing filter will remove unwanted signals above f s /2 in the input signal but the converter wideband noise will alias into the baseband. in the AD7884/ad7885, this noise is made up of sample-and-hold noise and a/d converter noise. the sample-and-hold section contrib- utes 51 v rms and the adc section contributes 59 v rms. these add up to a total rms noise of 78 v. this is the input referred noise in the 3 v analog input range. when operating in the 5 v input range, the input gain is reduced to 0.6. this means that the input referred noise is now increased by a factor of 1.66 to 120 v rms. figure 14 shows a histogram plot for 5000 conversions of a dc input using the AD7884/ad7885 in the 5 v input range. the analog input was set as close as possible to the center of a code transition. all codes other than the center code are due to the adc noise. in this case, the spread is six codes. 3000 0 2000 1000 code frequency (x 2) (x 1) (x) (x + 1) (x + 2) (x + 3) code figure 14. histogram of 5000 conversions of a dc input if the noise in the converter is too high for an application, it can be reduced by oversampling and digital filtering. this involves sampling the input at higher than the required word rate and then averaging to arrive at the final result. the very fast con- version time of the AD7884/ad7885 makes it very suitable for oversampling. for example, if the required input bandwidth is 40 khz, the AD7884/ad7885 could be oversampled by a factor of 2. this yields a 3 db improvement in the effective snr performance. the noise performance in the 5 volt input range is now effectively 85 v rms and the resultant spread of codes for 2500 conversions will be four. this is shown in figure 15. 1500 0 1000 500 code frequency (x 1) (x) (x + 1) (x + 2) code figure 15. histogram of 2500 conversions of a dc input using a 2 oversampling ratio
rev. d AD7884/ad7885 C12C dynamic performance with a combined conversion and acquisition time of 6 s, the AD7884/ad7885 is ideal for wide bandwidth signal processing applications. signal to (noise + distortion), total harmonic distort ion, peak harmonic or spurious noise and intermodu- lation distortion are all specified. figure 16 shows a typical fft plot of a 1.8 khz, 5 v input after being digitized by the AD7884/ad7885. 0 150 60 120 90 30 2048 point fft db f in = 1.8khz, 5v sine wave f sample = 163khz snr = 87db thd = 95db figure 16. AD7884/ad7885 fft plot effective number of bits the formula for snr (see terminology section) is related to the resolution or number of bits in the converter. rewriting the formula, below, gives a measure of performance expressed in effective number of bits (n). n = ( snr 1.76)/6.02 16 10 80 13 11 20 12 0 15 14 60 40 frequency khz effective number of bits figure 17. effective number of bits vs. frequency the effective number of bits for a device can be calculated from its mea sured snr. figure 17 shows a typical plot of ef fective number of bits versus frequency for the AD7884. the sampling frequency is 166 khz. microprocessor interfacing the AD7884/ad7885 is designed on a high speed process which results in very fast interfacing timing (data access time of 57 ns max). the AD7884 has a full 16-bit parallel bus, and the ad7885 has an 8-bit wide bus. the AD7884, with its paral- lel interface, is suited to 16-bit parallel machines whereas the ad7885, with its byte interface, is suited to 8-bit machines. some examples of typical interface configurations follow. AD7884 to mc68000 interface figure 18 shows a general interface diagram for the mc68000, 16-bit microprocessor to the AD7884. in figure 18, conversion is initiated by bringing csa low (i.e., writing to the appropriate address). this allows the processor to maintain control over the complete conversion process. in some cases it may be more desirable to control conversion independent from the processor. this can be done by using an external sampling timer. mc68000 AD7884 address decode logic convst cs rd db15 db0 r/ w data bus address bus a23 a1 d15 d0 dtack as csa csb figure 18. AD7884 to mc68000 interface once conversion has been started, the processor must wait until it is completed before reading the result. there are two ways of ensuring this. the first way is to simply use a software delay to wait for 6.5 s before bringing cs and rd low to read the data. the second way is to use the busy output of the ad7 884 to generate an interrupt in the mc68000. because of the nature of its interrupts, the mc68000 requires additi onal logic (not shown in figure 18) to allow it to be interrupted correctly. for full information on this, consult the mc68000 user s manual.
rev. d AD7884/ad7885 C13C AD7884 to 80286 interface the 80286 is an advanced high performance processor with special capabilities aimed at multiuser and multitasking systems. figure 19 shows an interface configuration for the AD7884 to such a system. note that only signals relevant to the AD7884 are shown. for the full 80286 configuration refer to the iapx 286 data sheet (basic system configuration). in figure 19 conversion is started by writing to a selected address and causing it cs2 to go low. when conversion is com- plete, busy goes high and initiates an interrupt. the processor can then read the conversion result. 82288 bus controller mrdc clk 82284 clock generator clk 8282 or 8283 latch 8286 or 8287 transceiver decode circuitry 8259a interrupt controller clk d 15 d 0 a23 a0 AD7884 rd cs convst db15 db0 busy ir 0 ir 7 memory read 80286 cpu cs1 cs2 figure 19. AD7884 interfacing to basic iapx 286 system ad7885 to 8088 interface the ad7885, with its byte (8 + 8) data format, is ideal for use with the 8088 microprocessor. figure 20 is the interface diagram. conversion is started by enabling csa . at the end of conversion, data is read into the processor. the read instructions are: mov ax, c001 read 8 msbs of data mov ax, c000 read 8 lsbs of data 8088 ad7885 address decode logic convst cs rd db7 db0 mn/ mx data bus address bus a15 a8 ad7 ad0 5v a0 hben rd stb 8282 ale io/ m csb csa figure 20. ad7885 to 8088 interface
rev. d AD7884/ad7885 C14C AD7884 to adsp-2101 interface figure 21 shows an interface between the AD7884 and the adsp-2101. conversion is initiated using a timer which allows very accurate control of the sampling instant. the AD7884 busy line provides an interrupt to the adsp-2101 when conversion is completed. the rd pulsewidth of the processor can be pro- grammed using the data memory wait state control register. the result can then be read from the adc using the follow- ing instruction: mr0 = dm (adc) where mr0 is the adsp-2101 mr0 register, and adc is the AD7884 address. adsp-2101 AD7884 address decode logic convst cs busy db15 db0 data bus address bus dma13 dma0 dmd15 dmd0 irqn en dms timer rd rd figure 21. AD7884 to adsp-2101 interface stand-alone operation if cs and rd are tied permanently low on the AD7884, then, when a conversion is completed, output data will be valid on the rising edge of busy . this makes the device very suitable for stand-alone operation. all that is required to run the device is an external convst pulse which can be supplied by a sample timer. figure 22 shows the AD7884 set up in this mode with the busy signal providing the clock for the 74hc574 3-state latches. timer AD7884 convst cs rd db15 db8 busy hben a0 74hc574 74hc574 clk clk db7 db0 figure 22. stand-alone operation digital feedthrough from an active bus it is very important when using the AD7884/ad7885 in a microprocessor-based system to isolate the adc data bus from the active processor bus while a conversion is being executed. this will yield the best noise performance from the adc. latches like the 74hc574 can be used to do this. if the device is connected directly to an active bus then the converter noise will typically increase by a factor of 30%.
rev. d AD7884/ad7885 C15C outline dimensions dimensions shown in inches and (mm). 28-lead cerdip (q-28) 28 114 15 0.610 (15.49) 0.500 (12.70) pin 1 0.005 (0.13) min 0.100 (2.54) max 15 0 0.620 (15.75) 0.590 (14.99) 0.018 (0.46) 0.008 (0.20) seating plane 0.225 (5.72) max 1.490 (37.85) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.015 (0.38) min 0.026 (0.66) 0.014 (0.36) 0.110 (2.79) 0.090 (2.29) 0.070 (1.78) 0.030 (0.76) 40-lead plastic dip (q-40) 40 120 21 0.620 (15.75) 0.510 (12.95) pin 1 0.005 (0.13) min 0.098 (2.49) max seating plane 0.225 (5.72) max 2.096 (52.23) max 0.200 (5.08) 0.125 (3.18) 0.026 (0.66) 0.014 (0.36) 0.100 (2.54) bsc 0.065 (1.65) 0.045 (1.14) 0.070 (1.78) 0.015 (0.38) 15 0 0.63 (16.00) 0.59 (14.93) 0.018 (0.46) 0.008 (0.20) 44-lead plcc (p-44a) 6 pin 1 identifier 7 40 39 17 18 29 28 top view (pins down) 0.695 (17.65) 0.685 (17.40) sq 0.656 (16.66) 0.650 (16.51) sq 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 0.020 (0.50) r 0.021 (0.53) 0.013 (0.33) 0.050 (1.27) bsc 0.63 (16.00) 0.59 (14.99) 0.032 (0.81) 0.026 (0.66) 0.180 (4.57) 0.165 (4.19) 0.040 (1.01) 0.025 (0.64) 0.025 (0.63) 0.015 (0.38) 0.110 (2.79) 0.085 (2.16) 0.056 (1.42) 0.042 (1.07)
rev. d C16C c01353C0C2/02(0) printed in u.s.a. AD7884/ad7885 revision history location page data sheet changed from rev. c to rev. d. addition of cerdip package to general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 j column added to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 cerdip added to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 edit to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 addition of q-28 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

▲Up To Search▲

Price & Availability of AD7884

	To Download AD7884 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .